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1/31 preliminary data july 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m29kw016e 16 mbit (1mb x16, uniform block) 3v supply lightflash? memory features summary n supply voltage Cv cc = 2.7v to 3.6v for read Cv pp = 11.4v to 12.6v for program and erase n access time: 90, 110ns n programming time C 9s per word typical C multiple word programming option (2s typical chip program) n erase time C 11s typical factory chip erase n uniform blocks C 8 blocks of 2 mbits n program/erase controller C embedded word program algorithms n 10,000 program/er ase cycles per block n electronic signature C manufacturer code: 0020h C device code : 88abh figure 1. packages tsop48 (n) 12 x 20mm tfbga48 (za) 6 x 9mm fbga so44 (m)
m29kw016e 2/31 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. tsop connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 address inputs (a0-a19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data inputs/outputs (dq8-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 reset (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ready/busy output (rb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 vss ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read/reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 word program command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 multiple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 program phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 block erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chip erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. multiple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . 11 figure 6. multiple word program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3/31 m29kw016e status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 vpp status bit (dq4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 alternative toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 multiple word program bit (dq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. multiple word program timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 table 8. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 14. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 15. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. so44 - 44 lead plastic small outline, 525 mils body width, package outline . . . . . . . . 24 table 17. so44 - 44 lead plastic small outline, 525 mils body width, package mechanical data . 24 figure 16. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . . . 25 table 18. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . 25 figure 17. tfbga48 6x9mm - 8x6 ball array, 0.80 mm pitch, bottom view package outline . . . . 26 table 19. tfbga48 6x9mm - 8x6 ball array, 0.80 mm pitch, package mechanical data. . . . . . . . 26 figure 18. tfbga48 daisy chain - package connections (top view through package) . . . . . . . . 27 figure 19. tfbga48 daisy chain - pcb connections (top view through package) . . . . . . . . . . . 28 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 table 21. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 22. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
m29kw016e 4/31 summary description the m29kw016e lightflash ? is a 16 mbit (1mb x16) non-volatile memory that can be read, erased and reprogrammed. read operations can be per- formed using a single low voltage (2.7 to 3.6v) supply. program and erase operations require an additional v pp (11.4 to 12.6) power supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into 8 uniform blocks that can be erased independently so it is possible to preserve valid data while old data is erased (see figures 2, block addresses). program and erase commands are written to the command interface of the memory. an on-chip program/erase con- troller (p/e.c.) simplifies the process of program- ming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the m29kw016e lightflash? features a new command, multiple word program, used to pro- gram large streams of data. it greatly reduces the total programming time when a large number of words are written to the memory at any one time. using this command the entire memory can be programmed in 2s, compared to 9s using the stan- dard word program. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is offered in so44, tsop48 (12 x 20mm) and tfbga48 (6 x 9mm, 0.8mm pitch) packages. the memory is supplied with all the bits erased (set to 1). figure 2. logic diagram note: rb not available on so44 package. table 1. signal names a0-a19 address inputs dq0-dq15 data inputs/outputs e chip enable g output enable w write enable rp reset rb ready/busy output (not available on so44 package) v cc supply voltage read v pp supply voltage program erase v ss ground nc not connected internally ai04371 20 a0-a19 dq0-dq15 v cc m29kw016e e v ss 16 g rp v pp rb w
5/31 m29kw016e figure 3. so connections figure 4. tsop connections g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 dq15 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 a19 rp a4 a7 ai04377 m29kw016e 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8 a18 w v pp dq3 dq9 dq2 a6 dq0 a3 dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 dq4 dq5 a7 dq7 ai04376b m29kw016e 12 1 13 24 25 36 37 48 dq8 a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 a15 a14 nc e a0 rp v pp nc v ss v cc v ss rb w nc
m29kw016e 6/31 figure 5. tfbga connections (top view through package) table 2. block addresses ai04373 6 5 4 3 2 1 v ss dq15 a15 a14 a12 dq3 dq11 dq10 a18 dq1 dq9 dq8 dq0 a6 a5 a7 g e a4 a3 dq2 dq6 dq13 dq14 a10 a9 a13 dq4 dq12 dq5 rp a11 dq7 a2 v ss a1 a16 g f e b a d c h nc v pp a17 a19 v cc a8 a0 nc rb w nc block number address range 8 e0000h-fffffh 7 c0000h-dffffh 6 a0000h-bffffh 5 80000h-9ffffh 4 60000h-7ffffh 3 40000h-5ffffh 2 20000h-3ffffh 1 00000h-1ffffh
7/31 m29kw016e signal descriptions see figure 2, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a19). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the program/erase con- troller. data inputs/outputs (dq0-dq7). the data in- puts/outputs outputs the data stored at the select- ed address during a bus read operation. during bus write operations they represent the com- mands sent to the command interface of the pro- gram/erase controller. data inputs/outputs (dq8-dq15). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memorys com- mand interface. reset (rp ). the reset pin can be used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset low, v il , for at least t plpx . after reset goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , which- ever occurs last. see the ready/busy output sec- tion, table 16 and figure 14, reset ac characteristics for more details. ready/busy output (rb ). the ready/busy pin is an open-drain output that can be used to identify when the memory array can be read. ready/busy is high-impedance during read mode and auto select mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high-impedance. see table 16 and figure 14, reset ac characteristics. during program or erase operations ready/busy is low, v ol . ready/busy will remain low during read/reset commands or hardware resets until the memory is ready to enter read mode. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. v cc supply voltage. the v cc supply voltage supplies the power for read operations. the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . v pp program supply voltage. v pp is both a power supply and write protect pin. the two func- tions are selected by the voltage range applied to the pin. the supply voltage v cc must be applied before the program supply voltage v pp . if v pp is in the range 11.4v to 12.6v it acts as a power supply pin for program and erase opera- tions. v pp must be stable until the program/erase algorithm is completed. if v pp is kept in a low voltage range (0v to 3.6v) v pp is seen as a write protect pin. in this case a voltage lower than v hh gives an absolute protec- tion against program or erase, while v pp in the range of v hh enables these functions (see table 12, dc characteristics for the relevant values). note that v pp must not be left floating or uncon- nected as the device may become unreliable. vss ground. the v ss ground is the reference for all voltage measurements.
m29kw016e 8/31 bus operations there are six standard bus operations that control the device. these are bus read, bus write, out- put disable, standby, automatic standby and electronic signature. see tables 3, bus opera- tions, for a summary. typically glitches of less than 5ns on chip enable or write enable are ig- nored by the memory and do not affect bus opera- tions. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 11, read mode ac waveforms, and table 13, read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 12 and 13, write ac waveforms, and tables 14 and 15, write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 12, dc characteristics. during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables 3, bus operations. table 3. bus operations note: 1. x = v il or v ih . 2. xx = v il , v ih or v hh 3. not necessary for auto select or read/reset commands. 4. when reading the status register during program or erase operations, v pp must be kept at v hh . operation e g w v pp address inputs a0-a19 data inputs/outputs dq15-dq0 bus read v il v il v ih xx (4) cell address data output bus write v il v ih v il v hh (3) command address data input output disable x v ih v ih x x hi-z standby v ih x x x x hi-z read manufacturer code v il v il v ih xx a0 = v il , a1 = v il , others v il or v ih 0020h read device code v il v il v ih xx a0 = v ih , a1 = v il , others v il or v ih 88abh
9/31 m29kw016e command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. refer to tables 4 and 5, for a summary of the com- mands. read/reset command. the read/reset command returns the memory to its read mode where it behaves like a rom or eprom, unless otherwise stated. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, be- tween bus write cycles before the start of a pro- gram or erase operation, to return the device to read mode. once the program or erase operation has started the read/reset command is no longer accepted. the read/reset command is executed regardless of the value of v pp (v il , v ih or v hh ). auto select command. the auto select command is used to read the manufacturer code and the device code. three consecutive bus write operations are required to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until a read/reset command is issued, all other commands are ignored. the auto select command is executed regardless of the val- ue of v pp (v il , v ih or v hh ). from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . word program command. the word program command can be used to pro- gram a word to the memory array. v pp must be set to v hh during word program. if v pp is set to ei- ther v il or v ih the command will be ignored, the data will remain unchanged and the device will re- vert to read/reset mode. the command requires four bus write operations, the final write operation latches the address and data in the internal state machine and starts the program/erase controller. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 6. bus read op- erations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. note that the program command cannot change a bit set at 0 back to 1. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from 0 to 1. multiple word program command the multiple word program command can be used to program large streams of data. it greatly reduces the total programming time when a large number of words are written to the memory at any one time. v pp must be set to v hh during multiple word program. if v pp is set to either v il or v ih the command will be ignored, the data will remain un- changed and the device will revert to read/reset mode. it has four phases: the setup phase to initiate the command, the program phase to program the data to the memory, the verify phase to check that the data has been correctly programmed and re- program if necessary and the exit phase. setup phase. the multiple word program com- mand requires three bus write operations to ini- tiate the command (refer to table 5, multiple word program command and figure 6, multiple word program flowchart). the status register toggle bit (dq6) should be checked to verify that the op- eration has started and the multiple word program bit (dq0) checked to verify that the p/e.c. is ready for the first word. program phase. the program phase requires n+1 cycles, where n is the number of words, to ex- ecute the programming phase (refer to table 5, multiple word program command and figure 6, multiple word program flowchart). three successive steps are required to issue and execute the program phase of the command. 1. the fourth bus write operation of the command latches the start address and the first word to be programmed. the status register multiple word program bit (dq0) should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address can remain the start address, be incremented or be any address in the same block, as the device automatically increments the address with each sucssesive bus write
m29kw016e 10/31 cycle. if the command is used to program in more than one block then the address must remain in the starting block as any address that is not in the same block as the start address terminates the program operation. the status register multiple word program bit (dq0) must be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. finally, after all words have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate the programming phase. the memory is now set to enter the verify phase. verify phase. the verify phase is similar to the program phase in that all words must be resent to the memory for them to be checked against the programmed data. if the check fails the p/e.c will try to reprogram the correct data. the p/e.c will remain busy until the correct data has been suc- cessfully programmed. the verify phase is man- datory. if the verify phase is not executed the programmed data cannot be guaranteed. three successive steps are required to execute the verify phase of the command. 1. use one bus write operation to latch the start address and the first word, to be verified. the status register multiple word program bit (dq0) should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be verified is latched with a new bus write operation. if any address that is not in the same block as the start address is given, the verify operation terminates. the status register multiple word program (dq0) must be read to check that the p/e.c. is ready for the next word. 3. finally, after all words have been verified, write one bus write operation to any address outside the block containing the start address, to terminate the verify phase. exit phase . read the status register to verify that dq6 has stopped toggling. if the verify phase is successfully completed the memory returns to the read mode. if the p/e.c. fails to reprogram a given location, the verify phase will terminate and error bit dq5 will be set in the status register. if the error is due to a v pp failure dq4 will also be set. if the operation fails a read/reset command must be issued to return the device to read mode. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 6. bus read operations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. note that the multiple word program command cannot change a bit set at 0 back to 1. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1. block erase command. the block erase command can be used to erase a block. it sets all of the bits in the block to 1. all previous data in the block is lost. v pp must be set to v hh during block erase. if v pp is set to either v il or v ih the command will be ig- nored, the data will remain unchanged and the de- vice will revert to read/reset mode. six bus write operations are required to select the block . the block erase operation starts the pro- gram/erase controller after the last bus write op- eration. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/erase controller has started the block erase operation. during the block erase operation the memory will ignore all commands. typical block erase times are given in table 6. all bus read operations dur- ing the block erase operation will output the sta- tus register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. chip erase command. the chip erase command can be used to erase the entire memory. it sets all of the bits in the mem- ory to 1. all previous data in the memory is lost. v pp must be set to v hh during chip erase. if v pp is set to either v il or v ih the command will be ig- nored, the data will remain unchanged and the de- vice will revert to read/reset mode. six bus write operations are required to issue the chip erase command and start the program/erase control- ler. during the erase operation the memory will ignore all commands. it is not possible to issue any com- mand to abort the operation. typical chip erase times are given in table 6. all bus read opera- tions during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode.
11/31 m29kw016e table 4. standard commands note: x dont care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. the command interface only uses a0-a10 and dq0-dq7 to verify the commands; a11-a19, dq8-dq15 are dont care. table 5. multiple word program command note: a bus read must be done between each write cycle where the data is programmed or verified, to read the status register and check that the memory is ready to accept the next data. not pa1 is any address that is not in the same block as pa1. x dont care, n = number of words to be programmed. table 6. program, erase times and program, erase endurance cycles note: 1. t a = 25c, v pp = 12v. table 7. multiple word program timings note: 1. mwp = multiple word program. command length bus write operations 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 word program 4 555 aa 2aa 55 555 a0 pa pd block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 phase length bus write operations 1st 2nd 3rd 4th 5th final -1 final add data add data add data add data add data add data add data program 3+n +1 555 aa 2aa 55 555 20 pa 1 pd1 pa1 pd2 pa1 pan not pa 1 x verify n+1 pa1 pd1 pa1 pd2 pa1 pd3 pa1 pd4 pa1 pd5 pa1 pan not pa 1 x parameter min typ (1) typical after 10k w/e cycles (1) max unit chip erase 11 25 120 s block erase (128 kwords) 1.5 6 s program (word) 9 250 s chip program (multiple word) 2 35 s chip program (word by word) 9 35 s program/erase cycles (per block) 10,000 cycles symbol parameter min typ max unit t mwp-setup mwp setup time 500 ns t mwp-prog mwp program time 9 250 s t mwp-tran mwp program to verify transition 2 10 20 s t mwp-end mwp verify to end transition 2 3 s
m29kw016e 12/31 figure 6. multiple word program flowchart note: 1. refer to table 7, multiple word program timings, for the values. write aah address 555h ai05554c start read status register yes no dq0 = 0? write 55h address 2aah write 20h address 555h write data1(pd 1 ) start address (pa 1 ) write data 2 (pd 2 ) address in start block yes no read status register write data n (pd n ) address in start block yes no read status register write xx any address not in start block read status register no write data1 (pd 1 ) start address (pa 1 ) write data 2 (pd 2 ) address in start block no read status register write data n (pd n ) address in start block read status register write xx any address not in start block yes write f0h address xx exit (read mode) dq0 = 0? dq0 = 0? dq0 = 0? dq0 = 0? dq0 = 0? read status register no dq6 toggling? dq5 = 1 dq4 = 0? yes fail, v pp error no program phase yes no dq0 = 0? yes setup time exceeded? exit ( setup failed ) no dq0 = 0? read status register no word program time exceeded? yes yes no word program time exceeded? yes no word program time exceeded? yes dq6 toggling? read status register no yes yes no fail error yes no setup phase verify phase exit phase read status register (t mwp-setup (1) ) (t mwp-prog (1) ) (t mwp-prog (1) ) (t mwp-prog (1) ) yes (t mwp-end (1) ) (t mwp-tran (1) )
13/31 m29kw016e status register bus read operations from any address always read the status register during program and erase operations. the bits in the status register are summarized in table 8, status register bits. data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion. the data polling bit is output on dq7 when the status register is read. during a word program operation the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the word program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its com- plement. the data polling bit is not available dur- ing a multiple word program operation. during erase operations the data polling bit out- puts 0, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. figure 7, data polling flowchart, gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from 0 to 1 to 0, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. figure 8, data toggle flowchart, gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to 1 when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to 0 back to 1 and attempting to do so will set dq5 to 1. a bus read operation to that ad- dress will show the bit is still 0. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1. v pp status bit (dq4). the v pp status bit can be used to identify if any program or erase operation has failed due to a v pp error. if v pp falls below v hh during any program or erase operation, the oper- ation aborts and dq4 is set to 1. if v pp remains at v hh throughout the program or erase operation, the operation completes and dq4 is set to 0. erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to 1. the erase timer bit is output on dq3 when the status reg- ister is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during block and chip erase op- erations. the alternative toggle bit is output on dq2 when the status register is read. during erase operations the toggle bit changes from 0 to 1 to 0, etc., with successive bus read operations to any address. once the operation completes the memory returns to read mode. if an erase operation fails and the error bit is set, the alternative toggle bit will continue to toggle with successive bus read operations to any ad- dress. the alternative toggle bit does not change if the addressed block has erased correctly. multiple word program bit (dq0). the multiple word program bit can be used to indicate whether the program/erase controller is active or inactive during multiple word program. when the pro- gram/erase controller has written one word and is ready to accept the next word, the bit is set to 0. status register bit dq1 is reserved.
m29kw016e 14/31 table 8. status register bits note: 1. unspecified data bits should be ignored. 2. dq2 toggles on any address during block or chip erase and after an erase error. figure 7. data polling flowchart figure 8. data toggle flowchart operation condition dq7 dq6 dq5 dq4 dq3 dq2 dq0 rb word program any address dq7 toggle 0 CC C C0 word program error v pp = v hh dq7 toggle 1 0 C C C 0 v pp < v hh dq7 toggle 1 1 C C C 0 block/ chip erase any address 0 toggle 0 C 1 toggle (2) C0 erase error v pp = v hh 0 toggle 1 0 1 toggle (2) C0 v pp < v hh 0 toggle 1 1 1 toggle (2) C0 multiple word program p/e.c. active C toggle 0 C C C 1 0 p/e.c. inactive, waiting for next word C toggle 0 C C C 0 1 multiple word program error v pp = v hh C toggle 1 0 C C 1 0 v pp < v hh C toggle 1 1 C C 1 0 read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq6 start read dq6 twice fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
15/31 m29kw016e maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 9. absolute maximum ratings note: 1. minimum voltage may undershoot to C2v for less than 20ns during transitions. 2. maximum voltage may overshoot to v cc +2v for less than 20ns during transitions. 3. maximum voltage may overshoot to 14.0v for less than 20ns during transitions. v pp must not remain at v hh for more than a total of 80hrs. symbol parameter min max unit t bias temperature under bias C50 125 c t stg storage temperature C65 150 c v io input or output voltage (1,2) C0.6 v cc +0.6 v v cc read supply voltage C0.6 4 v v pp program/erase supply voltage C0.6 13.5 v
m29kw016e 16/31 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 10, operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 10. operating and ac measurement conditions figure 9. ac measurement i/o waveform figure 10. ac measurement load circuit table 11. device capacitance note: sampled only, not 100% tested. parameter m29kw016e unit 90 110 min max min max v cc read supply voltage 2.7 3.6 2.7 3.6 v v pp program/erase supply voltage 11.4 12.6 11.4 12.6 v ambient operating temperature 0 70 0 70 c load capacitance (c l ) 30 30 pf input rise and fall times 10 10 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v ai05546 v cc 0v v cc /2 ai05547 c l c l includes jig capacitance device under test 25k w v cc 25k w v cc 0.1f symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
17/31 m29kw016e table 12. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v 100 a i cc3 supply current (program/erase) p/e.c. active 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = C100 a v cc C0.4 v v hh v pp program/erase voltage 11.4 12.6 v i hh1 v pp current (read/standby) v pp = v hh 100 a i hh2 v pp current (program/erase) p/e.c. active 10 ma v lko program/erase lockout supply voltage 1.8 2.3 v
m29kw016e 18/31 figure 11. read ac waveforms table 13. read ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29kw016e unit 90 110 t avav t rc address valid to next address valid e = v il , g = v il min 90 110 ns t avqv t acc address valid to output valid e = v il , g = v il max 90 110 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g = v il max 90 110 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 35 35 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 30 30 ns t ghqz (1) t df output enable high to output hi-z e = v il max 30 30 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns ai05548 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a19 g dq0-dq15 e telqv tehqx tghqz valid
19/31 m29kw016e figure 12. write ac waveforms, write enable controlled ai05549 e g w a0-a19 dq0-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl v pp tvphel
m29kw016e 20/31 table 14. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. not required in auto select or read/reset command sequences. symbol alt parameter m29kw016e unit 90 110 t avav t wc address valid to next address valid min 90 110 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 35 35 ns t dvwh t ds input valid to write enable high min 35 35 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 45 ns t ghwl output enable high to write enable low read mode min 0 0 ns read sr toggle bits min 10 10 ns t whgl t oeh write enable high to output enable low read mode min 0 0 ns read sr toggle bits in multiple word program min 20 20 ns read sr toggle bits other operations min 30 30 ns t whrl (1) t busy program/erase valid to rb low max 35 35 ns t vchel t vcs v cc high to chip enable low min 50 50 s t vphel (2) t vcs v pp high to chip enable low min 500 500 ns
21/31 m29kw016e figure 13. write ac waveforms, chip enable controlled ai05550 e g w a0-a19 dq0-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl v pp tvphwl
m29kw016e 22/31 table 15. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. not required in auto select or read/reset command sequences. symbol alt parameter m29kw016e unit 90 110 t avav t wc address valid to next address valid min 90 110 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 35 35 ns t dveh t ds input valid to chip enable high min 35 35 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 45 ns t ghel output enable high to chip enable low read mode min 0 0 ns read sr toggle bits min 10 10 ns t ehgl t oeh chip enable high to output enable low read mode min 0 0 ns read sr toggle bits in multiple word program min 20 20 ns read sr toggle bits other operations min 30 30 ns t ehrl (1) t busy program/erase valid to rb low max 35 35 ns t vchwl t vcs v cc high to write enable low min 50 50 s t vphwl (2) t vcs v pp high to write enable low min 500 500 ns
23/31 m29kw016e figure 14. reset ac waveforms table 16. reset ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter m29kw016e unit 90 110 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 0 ns t plpx t rp rp pulse width min 500 500 ns t plyh (1) t ready rp low to read mode max 10 10 s ai05551 rb w, rp tplpx tphwl, tphel, tphgl tplyh e, g trhwl, trhel, trhgl
m29kw016e 24/31 package mechanical figure 15. so44 - 44 lead plastic small outline, 525 mils body width, package outline note: drawing is not to scale. table 17. so44 - 44 lead plastic small outline, 525 mils body width, package mechanical data symb mm inches typ min max typ min max a 2.42 2.62 0.095 0.103 a1 0.22 0.23 0.009 0.010 a2 2.25 2.35 0.089 0.093 b 0.50 0.020 c 0.10 0.25 0.004 0.010 d 28.10 28.30 1.106 1.114 e 13.20 13.40 0.520 0.528 e 1.27 C C 0.050 C C h 15.90 16.10 0.626 0.634 l 0.80 C C 0.031 C C a 3 C C 3 C C n44 44 cp 0.10 0.004 so-b e n cp b e a2 d c l a1 a h a 1
25/31 m29kw016e figure 16. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package outline note: drawing is not to scale. table 18. tsop48 - 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n48 48 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
m29kw016e 26/31 figure 17. tfbga48 6x9mm - 8x6 ball array, 0.80 mm pitch, bottom view package outline note: drawing is not to scale. table 19. tfbga48 6x9mm - 8x6 ball array, 0.80 mm pitch, package mechanical data millimeters inches symbol typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 1.000 0.0394 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 4.000 C C 0.1575 C C ddd 0.100 0.0039 e 9.000 8.900 9.100 0.3543 0.3504 0.3583 e 0.800 C C 0.0315 C C e1 5.600 C C 0.2205 C C fd 1.000 C C 0.0394 C C fe 1.700 C C 0.0669 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C e1 e d1 d eb a2 a1 a bga-z00 ddd fd fe sd se e ball "a1"
27/31 m29kw016e figure 18. tfbga48 daisy chain - package connections (top view through package) ai05552b h g 5 4 3 d c e f a b 12 6
m29kw016e 28/31 figure 19. tfbga48 daisy chain - pcb connections (top view through package) ai05553b h g 5 4 3 d c e f a b 12 6 start point end point
29/31 m29kw016e part numbering table 20. ordering information scheme table 21. daisy chain ordering scheme devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m29kw016e 90 n 1 t device type m29k = lightflash ? operating voltage w = v cc = 2.7 to 3.6v device function 016e = 16 mbit (x16) speed 90 = 90 ns 110 = 110 ns package m = so44: n = tsop48: 12 x 20 mm za = tfbga48: 6 x 9mm - 0.80mm pitch temperature range 1 = 0 to 70 c option t = tape & reel packing example: m29k dcl3-16 t device type m29k daisy chain dcl3-16 = daisy chain level 3 for 16 mbit parts option t = tape & reel packing
m29kw016e 30/31 revision history table 22. document revision history date version revision details 09-oct-2001 -01 first issue 26-mar-2002 -02 lfbga changed to tfbga package. write ac characteristics t wlwh, t dvwh, t wlax, t ghwl, t whgl, t eleh, t dveh, t elax, t ghel and t ehgl modified. multiple word program description and flowchart clarified. document classed as product preview. 07-may-2002 -03 tfbga pin f6 changed to nc. multiple word program flowchart clarified, alternative toggle bit dq2 description clarified, status register bits table modified. document classed as preliminary data. 12-jul-2002 -04 figure 8 modified. 23-jul-2002 4.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 04 becomes 4.0). figure 6, multiple word program flowchart, modified; table 7, multiple word program timings, added.
31/31 m29kw016e information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequence s of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is grante d by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subje c to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are n o authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics lightflash is a trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unite d states. www.st.com

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